1. Field of the Invention
The invention relates in general to a system for debugging an integrated circuit (IC) design, and in particular to a debugging system that relates gate level simulation, emulation or IC testing results to a register transfer level design.
2. Description of Related Art
An IC designer initially creates a “register transfer level” (RTL) design, also called a “register transfer logic” design, describing a digital electronic circuit as a hierarchy of logic modules that transmit data signals to one another via registers or other clocked devices that store information between clock cycles. The RTL design typically uses high level expressions to describe the logical relationships between the input and output signals of each block of logic.
The designer uses a computer-aided synthesis tool to convert the RTL design into a gate level design describing the IC as a set of interconnected instances of components (“cells”) such as transistors, logic gates, memories and the like that carry out the logic described by the RTL design. A cell library, usually provided by IC fabricator, describes the structure and behavior of each cell. The designer then uses computer-aided layout tools to generate an IC placement and routing plan for guiding IC fabrication, the plan indicating the position and orientation of each cell within the IC and describing the layout of the conductive nets that are to interconnect the cells.
At each stage of the design process, the designer uses verification tools such as simulators and emulators to determine whether the IC described by an RTL or gate level design will behave as expected. As illustrated in FIG. 1, to test an IC design at the gate level using a simulator or an emulator 12, the designer supplies it with a testbench 10 including the RTL or gate level design and a signal specification describing the time-varying behavior of IC input signals and specifying the particular IC signals that are to be monitored during the simulation or emulation. The simulator or emulator 12 then produces a dump file 14 indicating the time-varying behavior of the monitored IC signals in response to the specified IC input signal behavior. A computer-based debugger 16 processes dump file 14 to produce waveform displays indicating the behavior of the monitored signals and processes the RTL or gate level design to produce a source code listing, schematic diagrams and other displays cross-referenced to signal behavior data to help a user detect signal errors and ascertain the sources of those errors within the RTL or gate level design.
IC test engineers commonly employ IC functional testers for testing an IC after fabrication. A functional tester monitors the response of various IC signals as it stimulates an IC with input signals having specified time-varying behavior. FIG. 2 depicts a typical prior art IC functional testing and debugging process. A test program 18 supplied to a tester 20 indicates the time varying behavior of input signals the tester is to supply to an IC under test 22 derived from a gate level design 23 and indicates the expected behavior of IC signals to be monitored. Test program 18 is often based on previously generated gate level simulator or emulator dump file 24 so that it as nearly as possible stimulates the IC using the same input signal pattern used by simulator or emulator test bench. As it tests IC 22, tester 20 typically produces pass/fail data 26 indicating when monitored signals state fail to match states predicted by the gate level dump file. A debugger 26 may then process gate level dump file 24 and pass/fail data 26 to produce waveform displays of the monitored signals and indicating when signals are of unexpected states. Debugger 26 may also generate listings or schematic diagrams or other displays that cross-reference the observed signals to the gate level design 23 to help the user debug the IC design.
An IC designer normally prefers to think of the IC in terms of the hierarchical RTL design because that is the design the designer created and is easiest to understand. As it converts the RTL design into a gate level design, a computer-aided synthesis tool replaces the easy to understand RTL description of the circuit logic with a gate level description of circuit logic that eliminates the hierarchal nature of the design and that is much more difficult for a designer to understand. When the designer uses debugger 16 of FIG. 1 to review simulator or emulation results of the RTL design, the debugger correlates the signal behavior provided in dump file 14 to the various signals that appear in the RTL design that is familiar to the designer and therefore somewhat easier to debug than the gate level design. However, when the designer or test engineer uses debugger 16 of FIG. 1 or debugger 26 of FIG. 2 to review simulation, emulation or IC test results, the debugger 16 or 26 correlates the signal behavior described by dump file 14 or test data 26 to the gate level design which is more complicated and less familiar to the designer or test engineer, and therefore more difficult to debug.